Testing the operation of an integrated circuit and determining that it is operating as desired has become increasingly difficult as integrated circuit complexity has increased. Adequate testing frequently requires the testing of internal circuits that are not directly accessible from the device's terminals. One technique known as built-in self test (“BIST”), is useful for faster, at-speed testing of circuits with large, regular structures such as in integrated circuit memories. BIST uses a small controller circuit on the chip to carry out tests on command and to provide the results to an external agent. BIST enables faster testing of large on-chip memory structures at the expense of additional area and power costs for the on-chip test logic. The architecture for memory BIST logic is designed to enable at-speed testing of the on-chip memories while making acceptable tradeoffs between power and chip area.
A digital voltmeter (“DVM”) is an integral component of an on-chip BIST block for measuring voltages of a low input resistance source with rail-to-rail range. The DVM can be implemented by an analog-to-digital converter (“ADC”) circuit. The DVM can be part of a larger block of an IC to perform intermittent and/or continuous voltage monitoring of certain nodes, e.g. bias, vtune, etc., in order to ensure that proper bias conditions are met. Another usage for the DVM is that it can be used as a sampler for low-speed (e.g., a few MHz) signals. The DVM can also be used by the BIST to test one or more nodes of the IC depending on the design of the IC.
However, a DVM typically uses an operational amplifier for such conversion, which is untenable for an on-chip BIST since operational amplifiers require a large amount of chip area. Additionally, a DVM can suffer from mismatch and gain errors with no means for calibration of the DVM. Therefore, due to these drawbacks, it is desirable to provide new circuits, methods, and systems for a DVM.